// 假设已有 interface 定义： aru_ub_rdgen_cfg_if, ub_rd_req_if, aru_ub_dat_if, aru_payload_if

module tb_top;
    // clock / reset
    logic clk;
    logic rst_n;

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    initial begin
        rst_n = 0;
        #20 rst_n = 1;
    end

    // interface instances (names must match types in module)
    is_instr_if is_instr_if_inst ();
    aru_ub_rdgen_cfg_if aru_ub_rdgen_cfg_if_inst ();
    aru_psb_rdgen_cfg_if aru_psb_rdgen_cfg_if_inst ();
    aru_arb_rdgen_cfg_if aru_arb_rdgen_cfg_if_inst ();

    aru_mux_cfg_if aru_mux_2_to_1_up_cfg_if_inst ();
    aru_mux_cfg_if aru_mux_1_to_4_up_cfg_if_inst ();
    aru_mux_cfg_if aru_mux_1_to_2_psb_cfg_if_inst ();
    aru_mux_cfg_if aru_mux_2_to_1_down_cfg_if_inst ();
    aru_mux_cfg_if aru_mux_1_to_4_down_cfg_if_inst ();
    aru_mux_cfg_if aru_mux_1_to_3_unary_cfg_if_inst ();

    aru_add_sub_cfg_if aru_add_sub_cfg_if_inst ();
    aru_max_min_cfg_if aru_max_min_cfg_if_inst ();
    aru_mul_cfg_if aru_mul_cfg_if_inst ();
    aru_div_cfg_if aru_div_cfg_if_inst ();

    aru_unary_cfg_if aru_neg_cfg_if_inst ();
    aru_unary_cfg_if aru_clamp_cfg_if_inst ();
    aru_unary_cfg_if aru_exp_cfg_if_inst ();
    aru_unary_cfg_if aru_sqrt_cfg_if_inst ();
    aru_unary_cfg_if aru_pow_cfg_if_inst ();
    aru_unary_cfg_if aru_recp_cfg_if_inst ();

    aru_reduce_cfg_if aru_reduce_cfg_if_inst ();

    aru_ub_wrgen_cfg_if aru_ub_wrgen_cfg_if_inst ();
    aru_gm_wrgen_cfg_if aru_gm_wrgen_cfg_if_inst ();
    aru_arb_wrgen_cfg_if aru_arb_wrgen_cfg_if_inst ();

    done_if arb_wr_done_if_inst ();
    done_if ub_wr_done_if_inst ();
    done_if gm_wr_done_if_inst ();
    done_if done_if_inst ();

    // DUT instantiation: connect using interface_instance.<modport>
    aru_instr_mngr dut (
        .clk(clk),
        .rst_n(rst_n),
        .u_is_aru_instr_if(is_instr_if_inst),
        .u_aru_ub_rdgen_cfg_if(aru_ub_rdgen_cfg_if_inst),
        .u_aru_psb_rdgen_cfg_if(aru_psb_rdgen_cfg_if_inst),
        .u_aru_arb_rdgen_cfg_if(aru_arb_rdgen_cfg_if_inst),
        .u_aru_mux_2_to_1_up_cfg_if(aru_mux_2_to_1_up_cfg_if_inst),
        .u_aru_mux_1_to_4_up_cfg_if(aru_mux_1_to_4_up_cfg_if_inst),
        .u_aru_mux_1_to_2_psb_cfg_if(aru_mux_1_to_2_psb_cfg_if_inst),
        .u_aru_mux_2_to_1_down_cfg_if(aru_mux_2_to_1_down_cfg_if_inst),
        .u_aru_mux_1_to_4_down_cfg_if(aru_mux_1_to_4_down_cfg_if_inst),
        .u_aru_mux_1_to_3_unary_cfg_if(aru_mux_1_to_3_unary_cfg_if_inst),
        .u_aru_add_sub_cfg_if(aru_add_sub_cfg_if_inst),
        .u_aru_max_min_cfg_if(aru_max_min_cfg_if_inst),
        .u_aru_mul_cfg_if(aru_mul_cfg_if_inst),
        .u_aru_div_cfg_if(aru_div_cfg_if_inst),
        .u_aru_neg_cfg_if(aru_neg_cfg_if_inst),
        .u_aru_clamp_cfg_if(aru_clamp_cfg_if_inst),
        .u_aru_exp_cfg_if(aru_exp_cfg_if_inst),
        .u_aru_sqrt_cfg_if(aru_sqrt_cfg_if_inst),
        .u_aru_pow_cfg_if(aru_pow_cfg_if_inst),
        .u_aru_recp_cfg_if(aru_recp_cfg_if_inst),
        .u_aru_reduce_cfg_if(aru_reduce_cfg_if_inst),
        .u_aru_ub_wrgen_cfg_if(aru_ub_wrgen_cfg_if_inst),
        .u_aru_gm_wrgen_cfg_if(aru_gm_wrgen_cfg_if_inst),
        .u_aru_arb_wrgen_cfg_if(aru_arb_wrgen_cfg_if_inst),
        .u_arb_wr_done_if(arb_wr_done_if_inst),
        .u_ub_wr_done_if(ub_wr_done_if_inst),
        .u_gm_wr_done_if(gm_wr_done_if_inst),
        .u_done_if(done_if_inst)
    );

    // （可选）在 tb 里驱动接口信号，或在接口内写 driver/monitor task/class
    initial begin
        #1000 $finish;
    end
endmodule
